CY8C56LP
Description
PSoC® 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through: 32-bit Arm® Cortex®-M3 core plus DMA controller and digital filter processor, at up to 80 MHz Ultra low power with industry's widest voltage range Programmable digital and analog peripherals enable custom functions Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip architecture for embedded control design.
Key Features
- Operating characteristics Voltage range: 1.71 to 5.5 V, up to 6 power domains Temperature range (ambient): -40 to 85 Extended temperature parts: -40 to 105 °C[1] °C DC to 80-MHz operation Power modes
- Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz
- 2-µA sleep mode
- 300-nA hibernate mode with RAM retention Boost regulator from 0.5-V input up to 5-V output
- Performance 32-bit Arm Cortex-M3 CPU, 32 interrupt inputs 24-channel direct memory access (DMA) controller 24-bit 64-tap fixed-point digital filter processor (DFB)
- Memories Up to 256 KB program flash, with cache and security features Up to 32 KB additional flash for error correcting code (ECC) Up to 64 KB RAM 2 KB EEPROM
- Digital peripherals Four 16-bit timer, counter, and PWM (TCPWM) blocks I2C, 1 Mbps bus speed USB face (2T.I0Dc#e1r0ti8fi4e0d0F3u2l)l-uSspienegdin(tFeSrn) a1l2oMscbilplastopre[2r]ipheral inter- Full CAN 2.0b, 16 Rx, 8 Tx buffers 20 to 24 universal digital blocks create any number of functions: (UDB), programmable to
- 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
- I2C, UART, SPI, I2S, LIN 2.0 interfaces
- Cyclic redundancy check (CRC)
